원문정보
Phase locked looped based fractional freqeuncy synthesizer for 60 GHz wireless communication
초록
영어
This paper presents a mm-wave fractional PLL frequency synthesizer that has a tuning range capable of covering the whole band for 60 GHz communication systems. The synthesizer operates at 20 GHz with phase noise of -58 and -96.2 dBc/Hz at in-band and 1-MHz frequency offset, respectively. The proposed PLL consists of mm-wave 16/17 pre-scalar, 4 bit controllable VCO with constant Kv, and I/Q LO distribution network. An accurate I/Q phase LO network is constructed using resonate loading poly-phase filters and current driving buffers. Implemented in a 90 nm CMOS technology, the PLL and LO network consume 30 mW and 10 mW power from a 1.2 V supply.
목차
I. 서론
II. 주파수 합성기와 LO Network의 구조 및 설계
III. 시뮬레이션 및 측정 결과
IV. 결론
감사의 글
참고문헌
