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영어

Implementing an algorithm into hardware platforms is generally not an easy task. The algorithm, typically described in a high-level specification language, must be translated into a low-level HDL language. The difference between models of computation (sequential versus fine-grained parallel) limits the efficiency of automatic translation. On the other hand, manual implementation is time-consuming, because the designer must take care of low-level details, and write test benches to test the implementation’s behaviour. This paper presents a global design method, from high level description to implementation. The first step consists of the description of an algorithm as a dataflow program using RVC-CAL language. The next step is the functional verification of this description using a software framework. The final step consists of an automatic generation of an efficient hardware implementation from the dataflow program. The objective is to spend the greater part of the conception time in an open source software platform. We use this method to quickly prototype and generate hardware implementation of a baseline part of the LAR coder, from an RVC-CAL description.