원문정보
보안공학연구지원센터(IJFGCN)
International Journal of Future Generation Communication and Networking
vol.3 no.3
2010.09
pp.1-12
피인용수 : 0건 (자료제공 : 네이버학술정보)
초록
영어
The delay and dispersion of the packet train have been widely used in most network measurement tools. The timestamp of the packet is critical for the measurement accuracy. However, timestamping performed either in the application or the kernel layer would be easily affected by the source and destination hosts especially in high-speed network. Therefore, to evaluate the impact of the timestamp precision on the measurement, a high accuracy timestamping hardware system (HATS) based on NetFPGA was designed and implemented. With HATS, the deviation of timestamp accuracy among the application, the kernel and the hardware layers was analyzed.
목차
Abstract.
1 Introduction
2 Platform Architecture
3 System Design
3.1 Reference NIC
3.2 Time Stamp
3.3 Synchronization Mechanism
4 System Implementation
4.1 Time Stamp Counter
4.2 Time Stamp
4.3 RAM
4.4 Registers
5 Experiment Design
5.1 Experimental Environment
5.2 Traffic Generation
5.3 Experiment Design
5.4 Data Collection and Metrics
6 Evaluation and Analysis
6.1 Preprocess
6.2 One-way Analysis of Variance
6.3 Relative Deviation Analysis
7 Related Work
8 Conclusions
References
1 Introduction
2 Platform Architecture
3 System Design
3.1 Reference NIC
3.2 Time Stamp
3.3 Synchronization Mechanism
4 System Implementation
4.1 Time Stamp Counter
4.2 Time Stamp
4.3 RAM
4.4 Registers
5 Experiment Design
5.1 Experimental Environment
5.2 Traffic Generation
5.3 Experiment Design
5.4 Data Collection and Metrics
6 Evaluation and Analysis
6.1 Preprocess
6.2 One-way Analysis of Variance
6.3 Relative Deviation Analysis
7 Related Work
8 Conclusions
References
저자정보
참고문헌
자료제공 : 네이버학술정보