원문정보
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초록
영어
Floating-point division is generally regarded as a low frequency, high latency operation in typical floating-point applications.So due to this not much development had taken place in this field. But nowadays floating point divider has become indispensable and increasingly important in many modern applications. Most of the previous implementation required much larger area and latencies. In this paper an area optimized design and implementation of a sequential and pipelined double precision floating point divider is presented. This design is then mapped onto an FPGA chip without utilizing any of its embedded features
목차
Abstract
1. Introduction
2. Previous work
3. Double precision floating point divider based on IEEE 754 binary floating point standard
4. Double precision floating point divider architecture
5. Pipelining of Double precision floating point divider
6. Implementation results
7. Future enhancement
8. Conclusion
9. References
1. Introduction
2. Previous work
3. Double precision floating point divider based on IEEE 754 binary floating point standard
4. Double precision floating point divider architecture
5. Pipelining of Double precision floating point divider
6. Implementation results
7. Future enhancement
8. Conclusion
9. References
저자정보
참고문헌
자료제공 : 네이버학술정보