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초록
영어
The main aim of this paper is to design and implement a high speed, low complexity and polymorphic architecture for reconfigurable folded wavelet filters. 5/3 wavelet results are incorporated into the 9/7 data path which reduces the number of adders compared to other solutions and also allows on the fly switching between the filters. The proposed work is to improve the speed of this reconfigurable architecture. This is accomplished by scheduling. A weight based scheduling algorithm has been used in this paper. This is an analysis method to improve inter task communication as well as data dependencies among tasks which will reduce the overall communication overhead and processing time.
목차
Abstract
1. Introduction
2. The polymorphic architecture
2.1. Lagrange Half Band Filter
2.2. Canonical Signed Digit
2.3. Reconfigurable hardware
3. Proposed work
3.1. Scheduling
4. Simulation result
5. Experimental results
6. Conclusions
7.References
1. Introduction
2. The polymorphic architecture
2.1. Lagrange Half Band Filter
2.2. Canonical Signed Digit
2.3. Reconfigurable hardware
3. Proposed work
3.1. Scheduling
4. Simulation result
5. Experimental results
6. Conclusions
7.References
키워드
저자정보
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자료제공 : 네이버학술정보