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논문검색

High-Speed Parallel Architecture of the Whirlpool Hash Function

초록

영어

Whirlpool hash function should be capable of processing the input data streams at high speeds. We propose a fully synchronous parallel pipelined architecture with ten stages of pipelining between rounds, and internal pipelining within each round stage.
The proposed architecture can tremendously improve the performance of Whirlpool hash function. Our final implementation can encrypt continuous bit streams seamlessly, achieving a throughput of 56.89 G bps, which is considerably high compared to existing implementations in literature.

목차

Abstract
 1. Introduction
 2. Proposed high-speed hardware architecture
 3. Performance comparison
 4. Conclusion
 References

저자정보

  • Deen Kotturi Cadence Design Systems
  • Seong-Moo Yoo ECE Dept, The Univ. of Alabama in Huntsville

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