earticle

영어

The design of a memory control chip is described which is intended for embedded operation in VLSI Chip for 3D image application. It consists of two SRAMs and memory controller. The two memories section and their address counters are being swapped from the storage to the call clock. The systems offers improved accuracy, repeatability, portability, and flexibility not available in current commercial systems. To reduced a chip, 4T(4 transistors) SRAM cells are used instead of the standard SRAM cells 6T (6 transistors) by which the leakage current is drastically reduced and low power is achieved. The layout of the memory chip is realized using Electric layout editor, the DRC and LVS is verified using Electric and post layout simulated with LT SPICE tool of computer.