원문정보
초록
영어
The idea of using multivariate polynomials as public keys has attracted several cryptographers, SFlash signature scheme is a variant of the Matsumoto and Imai multivariate public Key cryptosystem and selected by NESSIE Consortium. In this paper we describe a hardware implementation of SFlash based on bit-parallel architectures to achieve high speed circuits for operations on Finite Fields which can be efficiently used as an authentication unit in wireless devices, smart cards and RFID networks. We have proposed a new generalization to Karatsuba-Ofman multiplier as the core of the design. An ASIC chip can be realized with 78K gates counts and 2.8 mm2 die size with 0.35 mm CMOS technology, with a maximum clock frequency 140 MHZ, which takes about 21.5 ms to sign 259-Bits data.
목차
1. Introduction
2. Signature Algorithm
2.1. Algorithm Fields
2.2. Secret Parameter.
2.3. Signing Algorithm.
3. Composite Fields Multiplication.
3.1 Mastrovito architecture forGF(27 ) .
3.2. Multiplier Over Composite Field GF(27 )37 .
3.3 Modular reduction
3.4 Secret affine transformation
3.5 Mapping Function
4. Results
5. Conclusion
References
Authors