원문정보
초록
영어
As data transfer rates become higher, general processor is not competent for works with high computing intensity in wireless communication area. The other hand, existing baseband processors lack adaptive ability to support new applications and newer versions of existing application. Thus the paper puts forward a novel architecture of reconfigurable stream processor along with application-specific instruction set for software radio. The main goal of the processor is to point out an effective way to designing hardware of software radio with high computational performance and adaptive ability. We achieve this by analyzing multi-stream modalities of advanced wireless communication standards, such as 3G and WLAN. Simulation results show that the processor with powerful calculation capability can adapt to applications of wireless communication area easily.
목차
1. Introduction
2. Algorithms analysis
2.1. FFT
2.2. Rake Receiver
2.3. Viterbi
2.4. Turbo Coding
3. Configurable instruction set
4. Architecture of reconfigurable stream processor
4.1. Wireless communication stream
4.2. Architecture overview
4.3. Instruction of ReSP
5. Results
5.1. Arithmetic intensity and Hardware usage
5.2. Flexibility and adaptive computing
5.3. Computational performance
6. Conclusions
References