@article{ART002670554,
author={서범규 and 김진태},
title={A Low-Power 8-bit Switched Capacitor Convolution Engine Optimized for Artificial Neural Networks in 65nm CMOS},
journal={IDEC Journal of Integrated Circuits and Systems},
year={2019},
volume={5},
number={4},
pages={7-11},
doi={10.23075/jicas.2019.5.4.002}
}

TY - JOUR
AU - 서범규
AU - 김진태
TI - A Low-Power 8-bit Switched Capacitor Convolution Engine Optimized for Artificial Neural Networks in 65nm CMOS
T2 - IDEC Journal of Integrated Circuits and Systems
JO - IDEC Journal of Integrated Circuits and Systems
PY - 2019
VL - 5
IS - 4
PB - 반도체설계교육센터
SP - 7
EP - 11
AB - In this paper, we present a study on a neural network operator that performs low resolution, low power, and high efficiency convolution operations in analog domains. The proposed operator is consisted of multiplying DAC (MDAC) with integrator structure and successive-approximation ADC (SAR ADC). The memory access frequency is lower than that of the digital operation because the addition operation is performed while the multiplication operation is performed, and the information is stored in the form of charge on the opamp output terminal. A digital-input, digital-output calculator consisting of MDAC and ADC was designed using a 65nm CMOS process. The result of transistor-level simulation was 30.11uW of power at 33.3MHz, which is equivalent to 2.21TOPS/W. And it shows improved power efficiency than conventional digital convolution operator.
KW - Convolutional Neural Network, Deep Learning, Switched-Capacitor
DO - 10.23075/jicas.2019.5.4.002
ER -

서범규 and 김진태. 2019, "A Low-Power 8-bit Switched Capacitor Convolution Engine Optimized for Artificial Neural Networks in 65nm CMOS", IDEC Journal of Integrated Circuits and Systems, vol.5, no.4 pp.7-11. Available from: doi:10.23075/jicas.2019.5.4.002

서범규, 김진태 "A Low-Power 8-bit Switched Capacitor Convolution Engine Optimized for Artificial Neural Networks in 65nm CMOS" IDEC Journal of Integrated Circuits and Systems 5.4 pp.7-11 (2019) : 7.

서범규, 김진태. A Low-Power 8-bit Switched Capacitor Convolution Engine Optimized for Artificial Neural Networks in 65nm CMOS. 2019; 5(4), 7-11. Available from: doi:10.23075/jicas.2019.5.4.002

서범규 and 김진태. "A Low-Power 8-bit Switched Capacitor Convolution Engine Optimized for Artificial Neural Networks in 65nm CMOS" IDEC Journal of Integrated Circuits and Systems 5, no.4 (2019) : 7-11.doi: 10.23075/jicas.2019.5.4.002

서범규; 김진태. A Low-Power 8-bit Switched Capacitor Convolution Engine Optimized for Artificial Neural Networks in 65nm CMOS. IDEC Journal of Integrated Circuits and Systems, 5(4), 7-11. doi: 10.23075/jicas.2019.5.4.002

서범규; 김진태. A Low-Power 8-bit Switched Capacitor Convolution Engine Optimized for Artificial Neural Networks in 65nm CMOS. IDEC Journal of Integrated Circuits and Systems. 2019; 5(4) 7-11. doi: 10.23075/jicas.2019.5.4.002

서범규, 김진태. A Low-Power 8-bit Switched Capacitor Convolution Engine Optimized for Artificial Neural Networks in 65nm CMOS. 2019; 5(4), 7-11. Available from: doi:10.23075/jicas.2019.5.4.002

서범규 and 김진태. "A Low-Power 8-bit Switched Capacitor Convolution Engine Optimized for Artificial Neural Networks in 65nm CMOS" IDEC Journal of Integrated Circuits and Systems 5, no.4 (2019) : 7-11.doi: 10.23075/jicas.2019.5.4.002