@article{ART002653727,
author={장대광 and 김지훈 and 권영우},
title={Design of FET structure for high frequency in 65nm CMOS process},
journal={IDEC Journal of Integrated Circuits and Systems},
year={2016},
volume={2},
number={3},
pages={1-6},
doi={10.23075/jicas.2016.2.3.001}
}

TY - JOUR
AU - 장대광
AU - 김지훈
AU - 권영우
TI - Design of FET structure for high frequency in 65nm CMOS process
T2 - IDEC Journal of Integrated Circuits and Systems
JO - IDEC Journal of Integrated Circuits and Systems
PY - 2016
VL - 2
IS - 3
PB - 반도체설계교육센터
SP - 1
EP - 6
AB - New designs of FET are proposed with built-in based and all revised transistor for lower resistance of gate and lower capacitances of Cgd to design Millimeter-wave Power Amplifier (PA) for high consistency with simulation. Measured maximum available gain is 9.41dB at 2m x24 all revised type transistor. The driving voltage of FET is 1.2V and gate voltage is 1V in 65nm normal CMOS process.
KW -
DO - 10.23075/jicas.2016.2.3.001
ER -

장대광, 김지훈 and 권영우. 2016, "Design of FET structure for high frequency in 65nm CMOS process", IDEC Journal of Integrated Circuits and Systems, vol.2, no.3 pp.1-6. Available from: doi:10.23075/jicas.2016.2.3.001

장대광, 김지훈, 권영우 "Design of FET structure for high frequency in 65nm CMOS process" IDEC Journal of Integrated Circuits and Systems 2.3 pp.1-6 (2016) : 1.

장대광, 김지훈, 권영우. Design of FET structure for high frequency in 65nm CMOS process. 2016; 2(3), 1-6. Available from: doi:10.23075/jicas.2016.2.3.001

장대광, 김지훈 and 권영우. "Design of FET structure for high frequency in 65nm CMOS process" IDEC Journal of Integrated Circuits and Systems 2, no.3 (2016) : 1-6.doi: 10.23075/jicas.2016.2.3.001

장대광; 김지훈; 권영우. Design of FET structure for high frequency in 65nm CMOS process. IDEC Journal of Integrated Circuits and Systems, 2(3), 1-6. doi: 10.23075/jicas.2016.2.3.001

장대광; 김지훈; 권영우. Design of FET structure for high frequency in 65nm CMOS process. IDEC Journal of Integrated Circuits and Systems. 2016; 2(3) 1-6. doi: 10.23075/jicas.2016.2.3.001

장대광, 김지훈, 권영우. Design of FET structure for high frequency in 65nm CMOS process. 2016; 2(3), 1-6. Available from: doi:10.23075/jicas.2016.2.3.001

장대광, 김지훈 and 권영우. "Design of FET structure for high frequency in 65nm CMOS process" IDEC Journal of Integrated Circuits and Systems 2, no.3 (2016) : 1-6.doi: 10.23075/jicas.2016.2.3.001